1. Field of the Invention
The present invention relates to a testing apparatus and a testing method for determining pass/fail of a device under test (“DUT”). More particularly, the present invention relates to a testing apparatus and a testing method for performing a test on a device such as a serial communication device or a serial I/O device with a loop-back configuration.
2. Description of the Related Art
Conventionally, a loop-back testing method using so-called ATE (Automatic Test Equipment) system is known. The loop-back testing is a testing for injecting a jitter into an output signal of a DUT and inputting the signal to an input pin of the DUT by feedback.
For example, M. Shimanouchi proposes a loop-back testing method using the configuration shown in FIG. 17 (M. Shimanouchi, “New Paradigm for Signal Paths in ATE Electronics are Needed for Serialcom Device Testing”, ITC Proceedings, pp. 903–912, 2002).
According to the method, a loop-back testing is performed via a pin electronics 420 for connecting a tester main frame 410 and a DUT 200. The pin electronics 420 includes a plurality of pin cards including a driver 422, a comparator 424, and a selecting circuit 426. The method performs the loop-back testing by using four (4) pin cards.
Each of the four pin cards is connected to an input terminal Rx and an output terminal Tx of the DUT 200, and an input terminal and an output terminal of a deterministic jitter injecting unit 430. The deterministic jitter injecting unit 430 is a circuit which includes a cable for injecting a data dependent jitter (a deterministic jitter) and the like and injects the deterministic jitter into a received signal.
The comparator 424-4 of the pin card connected to the output terminal Tx of the DUT 200 receives an output signal from the output terminal Tx. Then, the selecting circuit 426-3 of the pin card connected to the input terminal of the deterministic jitter injecting unit 430 selects the output signal output by the comparator 424-4 and provides the corresponding driver 422-3 with the output signal. The driver 422-3 provides the deterministic jitter injecting unit 430 with the received output signal and the deterministic jitter injecting unit 430 injects a deterministic jitter into the output signal. The output signal into which the deterministic jitter is injected is input to the input terminal Rx of the DUT 200 by feedback via the comparator 424-2, the selecting circuit 426-1, and the driver 422-1. By this configuration, the loop-back testing is performed.
Further, B. Laquai etc. propose a loop-back testing method based on a passive filter technology (US2002/0174159A1)
However, the testing method shown in FIG. 17 inputs the output signal of the DUT 200 by feedback via the driver 422 of the pin electronics 420, the comparator 424, etc. Thus, the number of circuit components through which the feedback signal passes increases and it is impossible to perform accurately a testing on the DUT 200 with a high data rate. Further, since it is required to provide the cable for injecting the deterministic jitter and the like on a performance board on which an arrangement area of the circuit components is limited, it is hard to perform a testing on a multi-lane device including signal paths arranged in a row of several tens to several hundreds. Further, since four pin cards are used per one lane, there is a problem that a great number of pin cards are required in case of performing a loop-back testing on a DUT 200 with multi-lane.
Further, according to the B. Laquai's method, a second-order filter is used to generate the deterministic jitter. However, in case of using the second-order filter, the timing of a signal is delayed and the amplitude level of the signal is reduced due to an attenuation term of a response characteristic of the second-order filter. Thus, performing the loop-back testing by injecting deterministic jitter using this method makes a jitter tolerance estimate of the DUT being underestimated.